The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have reached the 17ps barrier. This has resulted in high-speed design problems. Even if a design is for moderate frequency, the edge rates can cause it to reflect the high-speed effects.
This course provides participants with the tools for recognizing the problems with any proposed high-speed design. Students learn design rules and design processes that insure the PCB will function properly at the prototype stage. Instruction emphasizes cost-competitive design without sacrificing high-speed integrity.
The course benefits digital design engineers, design managers, test engineers, EMI/EMC engineers, IC digital logic designers, project managers of high-speed designs, communication engineers, and military digital engineers. No advanced math is required, although participants will find it helpful to bring a scientific calculator to the course. Instruction presents course material at a technical level that provides experienced designers with information to design and lay out a high-speed PCB that meets signal integrity (SI) and EMI.
Applies Towards the Following Certificates
- Study Abroad at UCLA Program : Required